Technical Field
The present invention relates to semiconductor devices and, more particularly, to the use of III-V-type and IV-type semiconductor devices on a single chip.
Description of the Related Art
III-V compound semiconductors, such as gallium arsenide, indium gallium arsenide, indium arsenide, and indium antimonide, may be used in transistor devices using complementary metal oxide semiconductor (CMOS) processes. While such devices have been shown, it is challenging to form III-V-based devices on the same chip as IV-based devices.
One challenge arises due to the relative volatility of III-V semiconductors. Whereas IV-type semiconductors (such as, e.g., silicon and silicon germanium) are stable at high temperatures, III-V-type semiconductors may be damaged by high-temperature processes that conventional semiconductors would withstand.
One conventional approach is to use stacked, three-dimensional CMOS devices, with n-type field effect transistors (FETs) and p-type FETs on separate layers. Such approaches can provide III-V-based devices and IV-based devices on the respective layers, but the cost may be prohibitively high and it can be difficult to achieve high performance and reliability due to the complicated fabrication processes.
Another conventional approach uses IV-based p-type FETs and III-V-based n-type FETs on a given chip, but with the same gate dielectric for each. This does not provide the ability to separately optimize the gate stack properties (such as, e.g., leakage, threshold voltage, performance, reliability, etc.) of each device type.